Contents for 2016 can be found here
Version 4.5.20 release on 06/01/2017
- enhancement: CDL netlisting combined into single dialog. Both flat and hierarchical netlisting will use symbol view NLPDeviceFormat for pin order list, if a symbol view exists.
- enhancement: Schematic Display Options dialog has 'Instance Names' field which allows setting instance names to be 'Preserve' or 'Force Spice compatible'. The former will keep instance names as-is during Check. The latter will change the prefix character to be spice-compatible, depending on the "type" property of the instance master.
- enhancement: Export CDL checks the last extracted date of all cellviews hierarchically from the current cellView down.
- enhancement: Export Verilog does not escape identifiers that don't need to be escaped.
- enhancement: Export Verilog can now netlist hierarchical schematics.
- bugfix: fixed an issue where creating a PCell instance with properties which do nopt exist as formal parameters of the python function for the PCell would cause an error.
- enhancement: geomEnclose() added optional 'flags' parameter for 'abut' flag. Else abutment of edges is considered a violation.
Version 4.5.21 release on 15/01/2017
- bugfix: CDL flattener now does not require a '/' character to delimit pins from subckt name in a subckt call.
- enhancement: Added cell name mapping to OASIS import/export.
Version 4.5.22 release on 22/01/2017
- bugfix: removed error if netlist had extra spaces at end of line in Generate Layout.
- bugfix: map devices command in netlist window now removes row that is selected, rather than last row.
- bugfix: map devices command in netlist window allows selection of row rather than individual items.
- bugfix: map devices command in netlist window did not update underlying data if rows were removed.
- bugfix: map devices command in netlist window did not map according to instances correctly.
- bugfix: querying PCell properties gave spurious warnings about not being able to find python module in PYTHONPATH entries.
Version 4.5.23 release on 27/01/2017
- enhancement: New Gemini option -P. If used together with -w (report property mismatches), it will match by device properties. If not used, the default will be used, i.e. matching by nets/devices but not considering properties, which can result in a netlist match, but property mismatch. Use of this option may slow matching.
- enhancement: New Gemini option -L. If used and the netlist has a top level .subckt, the pins are used as initial equivalence nodes. Mismatching name of number of nodes between the two netlists will be reported.
- enhancement: LEF reader now reports first 10 ports missing port shapes, then continues silently to avoid excessive errors if well taps are used.
- bugfix: Fixed some dialog layout issues on Mac.
Version 4.5.24 release on 05/02/2017
- bugfix: Fixed a crash when stretching a starting or ending segment of a MPP
- enhancement: Create/Move/Stretch of shapes can use layer colour/fill rather than outline yellow.
- enhancement: Online DRC spacing check performed when creating / moving / stretching shapes. Requires layer minSpace attribute set in technology file.
Version 4.5.25 release on 12/02/2017
- bugfix: Fixed a crash when e.g. moving labels.
- bugfix: Fixed a bug in hierarchical netlist flattening (e.g. when running LVS). The flattener ommitted the *.SCALE keyword from the netlist, so Gemini thinks all dimensions are in microns, and so a width of e.g. 1u is read as 1e-12 - and hence showed as zero in the property comparison report.
- enhancement: Various DRC check enhancements
- enhancement: Saving a cell now checks if the existing library version is less than the current library version, if so updates the existing library. This gets round a potential problem if users save cells using a newer version of Glade to a library created with an older version, without saving the whole lib.
- bugfix: fixed a bug in online DRC with paths in OpenGL mode where the halo was shown incorrectly.
- bugfix: fixed a bug in create MPP which could cause vertices to be reordered in OpenGL mode.
- enhancement: Schematic Create Pin dialog remembers previous direction/use.
- bugfix: fixed a bug that could occasionally cause a crash when viewing DRC error markers.
Version 4.5.26 release on 19/02/2017
- bugfix: Fixed a potential crash when using the Verify->DRC->View Errors... error dialog and clicking on 'Next' or 'Prev'.
- enhancement: Verify->DRC->View Errors... now uses highlighting to indicate the current error marker (shown in purple). Use Selection Options 'Dim unhilited objects' to make the current violation clearer.
- enhancement: Import Cadence techfile no reads std. via definitions.
- bugfix: Fixed a bug descending hierarchy.
- bugfix: fixed a bug using hierarchy browser to descend/ascend hierarchy.
- fixed an occasional crash after a design window was closed, e.g. when deleting a cell/cellView in the library browser.
- fixed a crash is chop command given with a zero width or height chop rectangle.
- fixed an issue writing GDS where instances could have master cells in other libraries.
- fixed an issue in OpenGL mode where instances could not be moved using the move cmd.
- allow use of '\n' character sequence in NLP label expressions to cause newlines in displayed label text.
Version 4.5.27 release on 26/02/2017
- bugfix: Fix a potential crash for multiline schematic labels.
- bugfix: Fix an issue where property display flag was getting initialised to false when creating instances.
- bugfix: Fixed some issues drawing text in schematics.
- bugfix: Fixed a crash when undoing a delete of certain objects.
- enhancement: improved symbol editor Check cmd. Now removes nets and pins which have no shape.
- bugfix: Shorted resistors would give an error. Now they are preserved on extraction.
- bugfix: Windows pathnames given in e.g. DRC or LPE dialog could give file not found errors if they contained escaped characters e.g. user\test would see the \t as a tab character.
Version 4.5.28 release on 06/03/2017
- enhancement: Added schematic check options dialog.
- bugfix: Floorplan->Place updated so can read DEF 5.8
- bugfix: Fixed a schematic check bug that could result in floating pins.
- bugfix: Fixed a crash when Next violation clicked on in view DRC markers if no violations remaining.
- enhancement: Extract commands e.g. extractMOS() now search the list of open libraries for the extraction pcell, rather than just the current cellView's library.
Version 4.5.29 release on 13/03/2017
- bugfix: fixed a bug that could cause occasional missing DRC violations.
- bugfix: view marker errors zooms to bbox of highlighted shape, rather than a bbox including (0,0)
- enhancement: made schematic check options dialog a menu item; options are saved and maintained during a session.
- bugfix: check schematic for floating pins caused pin shapes to move if error.
Version 4.5.30 release on 24/03/2017
- bugfix: fixed a display issue with schematics displaying NLP labels with linefeed (\n) characters.
- enhancement: spaces can be entered in NLP expressions using '\s'
- enhancement: schematic check for shorted output pins.
- enhancement: Gemini now reduces series RLC and parallel RLC. Devices must be of the same model type. Values are summed (series RL, parallel C) or reciprocals added (parallel RL, series C). The option -a controls series reduction, -b controls parallel reduction.
- enhancement: Export CDL loads/saves options for global nets, switchList and stopList to settings file.
- enhancement: LVS dialog now saves option state during session.
- enhancement: global nets (ones ending with '!') handled in the export CDL and LVS dialogs.
- bugfix: fixed a bug in CDL flattener where the *.SCALE was always written as MICRON, which could cause LVS to give property errors.
- enhancement: LVS now writes a <cellName>.lvs report file to the working directory containing the gemini output.
- enhancement: LVS now will take a schematic view instead of a netlist file if required. The schematic is automatically netlisted and flattenedprior to running Gemini.
Version 4.5.31 release on 30/03/2017
- enhancement: Deleting a wire in schematics deletes any solder dots at the ends of the wire.
- bugfix: edit bindkeys not working correctly.
- bugfix: fixed a bug smashing series resistors.
- enhancement: Added generate layout menu for schematic to layout, similar to netlist to layout.
- enhancement: Generate layout from schematic / netlist understands spice syntax for properties e.g. w=2u, r=10k.
- bugfix: fixed an occasional crash moving devices when DRD mode checking is on.
- bugfix: geomArea() reported incorrectly for shapes with holes.
- enhancement: geomSpace / geomSpace2 with width argument now also has a length value. Only parallel run lengths > length are checked. This avoids issues with perpendicular tracks.
- enhancement: Wire entry in schematics now supports additional snap options: HV (horizontal first), VH (Vertical first), horizontal, vertical.
Version 4.5.32 release on 07/04/2017
- enhancement: schematic device instances can be grouped for layout generation. Selected devices are assigned to a named group, groups can be added to, removed from or deleted. Grouped devices are placed together in a grid.
- enhancement: Layout generation now generates boundary shape with either square shaped based on device area and utilisation, or can have fixed W / H / W+H.
- enhancement: Layout generation has a pin editor allowing pin width/side/layer to be controlled.
- enhancement: Create Wire and Create Path commands have extra snapping modes. In addition to 90/45/any angle there is now Horizontal first then vertical, Vertical first then horizontal, Horizontal only and Vertical only.
- bugfix: Querying and changing an array of PCell instances collaped the array into a single instance. Now the array is preserved correctly.
- bugfix: Deleting a property using the Query dialog didn't delete the actual property, only the entry in the dialog. Now it deletes the property and gives info on what was deleted.
- bugfix: Deleting a cellView in the library browser would close all open cells with the same name. Now only closes the matching cellView.
Version 4.5.33 release on 10/04/2017
- enhancement: When creating a new wire, it the start or end coincides with the start or end of an existing wire, the two wires will be merged.
- enhancement: Gemini LVS will match R/L/C devices by L/W if the devices do not have a value (resistance etc)
- enhancement: Schematic Layout Generation now has an 'Edit Group' command which allows you to set the pattern (a 2D grid) for placement of the devices in the group.
- enhancement: Schematic Layout Generation now snaps instance origins to the layout grid.
- bugfix: Add Marker command added a marker when Apply was clicked, but not when OK was clicked.
- bugfix: rounding error when inserting vertical edges that intercepted with edges non-manhattan edges could cause boolean engine errors.
Version 4.5.34 release on 21/04/2017
- bugfix: ruler snap angle change would cause existing rulers to change.
- enhancement: create group and rename group in schematics warns if an attempt is made to create or rename to an existing group name.
- bugfix: when reducing series RLC devices in LVS, a port could be removed if it had only 1 connection to a device.
- bugfix: adding a wire created a solder dot at start and finish.
- bugfix: Create Instance could go into infinite loop on placing an instance in a cellView.
Copyright © Peardrop Design 2016.