MOSFETs
General form
MXXXXXXX ND NG NS NB MNAME <L=VAL> <W=VAL> <AD=VAL> <AS=VAL> + <PD=VAL> <PS=VAL> <NRD=VAL> <NRS=VAL> <OFF> + <IC=VDS, VGS, VBS> <TEMP=T> <M=N>
Examples
M1 24 2 0 20 TYPE1 M31 2 17 6 10 MODM L=5U W=2U M1 2 9 3 0 MOD1 L=10U W=5U AD=100P AS=100P PD=40U PS=40U
ND, NG, NS, and NB are the drain, gate, source, and bulk (substrate) nodes, respectively. MNAME is the model name. L and W are the channel length and width, in meters. AD and AS are the areas of the drain and source diffusions, in meters2. Note that the suffix U specifies microns (1e-6 m) and P sq-microns (1e-12 m2). If any of L, W, AD, or AS are not specified, default values are used. The use of defaults simplifies input file preparation, as well as the editing required if device geometries are to be changed. PD and PS are the perimeters of the drain and source junctions, in meters. NRD and NRS designate the equivalent number of squares of the drain and source diffusions; these values multiply the sheet resistance RSH specified on the .MODEL control line for an accurate representation of the parasitic series drain and source resistance of each transistor. PD and PS default to 0.0 while NRD and NRS to 1.0. OFF indicates an (optional) initial condition on the device for dc analysis. The (optional) initial condition specification using IC=VDS, VGS, VBS is intended for use with the UIC option on the .TRAN control line, when a transient analysis is desired starting from other than the quiescent operating point. See the .IC control line for a better and more convenient way to specify transient initial conditions. The (optional) TEMP value is the temperature at which this device is to operate, and overrides the temperature specification on the .OPTION control line. The temperature specification is ONLY valid for level 1, 2, 3, and 6 MOSFETs, not for level 4 or 5 (BSIM) devices.
M=N, the multiplier, puts N identical devices in parallel. They are named after the device with .0, .1 and so on, so M1 d g s b nch w=1u l=1u m=4 makes m1.0 to m1.3.
Parameters: MOSFET level 1 (Shichman-Hodges), MOSFET level 2 (MOS2), MOSFET level 3 (MOS3), MOSFET level 4 (BSIM1), MOSFET level 5 (BSIM2), MOSFET level 6 (MOS6), MOSFET level 8 (BSIM3 version 3.3.0), MOSFET level 14 (BSIM4)
MOSFET Models (NMOS/PMOS)
Spice3f5 provides eight MOSFET device models, which differ in the formulation of the I-V characteristic. The variable LEVEL on the .MODEL line specifies the model to be used:
| LEVEL | model | parameters |
|---|---|---|
| 1 | Shichman-Hodges | MOS1 |
| 2 | MOS2 (as described in [1]) | MOS2 |
| 3 | MOS3, a semi-empirical model (see [1]) | MOS3 |
| 4 | BSIM (as described in [3]) | BSIM1 |
| 5 | new BSIM (BSIM2; as described in [5]) | BSIM2 |
| 6 | MOS6 (as described in [2]) | MOS6 |
| 8 (or 49) | BSIM3 version 3.3.0 | BSIM3 |
| 14 (or 54) | BSIM4 | BSIM4 |
If LEVEL is not given, BSIM4 (level 14) is used; note that this differs from Berkeley Spice3, where the default was level 1. The level may be written as a floating point number, such as LEVEL = 4.00000E+000; it is rounded to the nearest whole number. Any other level gives the warning illegal argument to 'level' - BSIM4 assumed, and BSIM4 is used.
The dc characteristics of the level 1 through level 3 MOSFETs are defined by the device parameters VTO, KP, LAMBDA, PHI and GAMMA. These parameters are computed by SPICE if process parameters (NSUB, TOX, ...) are given, but user-specified values always override. VTO is positive (negative) for enhancement mode and negative (positive) for depletion mode N-channel (P-channel) devices. Charge storage is modeled by three constant capacitors, CGSO, CGDO, and CGBO which represent overlap capacitances, by the nonlinear thin-oxide capacitance which is distributed among the gate, source, drain, and bulk regions, and by the nonlinear depletion-layer capacitances for both substrate junctions divided into bottom and periphery, which vary as the MJ and MJSW power of junction voltage respectively, and are determined by the parameters CBD, CBS, CJ, CJSW, MJ, MJSW and PB. Charge storage effects are modeled by the piecewise linear voltages-dependent capacitance model proposed by Meyer. The thin-oxide charge-storage effects are treated slightly different for the LEVEL=1 model. These voltage-dependent capacitances are included only if TOX is specified in the input description and they are represented using Meyer's formulation.
There is some overlap among the parameters describing the junctions, e.g. the reverse current can be input either as IS (in A) or as JS (in A/m2). Whereas the first is an absolute value the second is multiplied by AD and AS to give the reverse current of the drain and source junctions respectively. This methodology has been chosen since there is no sense in relating always junction characteristics with AD and AS entered on the device line; the areas can be defaulted. The same idea applies also to the zero-bias junction capacitances CBD and CBS (in F) on one hand, and CJ (in F/m2) on the other. The parasitic drain and source series resistance can be expressed as either RD and RS (in ohms) or RSH (in ohms/sq.), the latter being multiplied by the number of squares NRD and NRS input on the device line.
A discontinuity in the MOS level 3 model with respect to the KAPPA parameter has been detected (see [10]). The supplied fix has been implemented in Spice3f2 and later. Since this fix may affect parameter fitting, the option "BADMOS3" may be set to use the old implementation (see the section on simulation variables and the ".OPTIONS" line). SPICE level 1, 2, 3 and 6 parameters:
| name | parameter | units | default | example |
|---|---|---|---|---|
| LEVEL | model index | - | 14 (BSIM4) | |
| VTO | zero-bias threshold voltage (VTO) | V | 0.0 | 1.0 |
| KP | transconductance parameter | A/V2 | 2.0e-5 | 3.1e-5 |
| GAMMA | bulk threshold parameter (γ) | V1/2 | 0.0 | 0.37 |
| PHI | surface potential (φ) | V | 0.6 | 0.65 |
| LAMBDA | channel-length modulation (MOS1 and MOS2 only) (λ) | 1/V | 0.0 | 0.02 |
| RD | drain ohmic resistance | Ω | 0.0 | 1.0 |
| RS | source ohmic resistance | Ω | 0.0 | 1.0 |
| CBD | zero-bias B-D junction capacitance | F | 0.0 | 20fF |
| CBS | zero-bias B-S junction capacitance | F | 0.0 | 20fF |
| IS | bulk junction saturation current (IS) | A | 1.0e-14 | 1.0e-15 |
| PB | bulk junction potential | V | 0.8 | 0.87 |
| CGSO | gate-source overlap capacitance per meter channel width | F/m | 0.0 | 4.0e-11 |
| CGDO | gate-drain overlap capacitance per meter channel width | F/m | 0.0 | 4.0e-11 |
| CGBO | gate-bulk overlap capacitance per meter channel length | F/m | 0.0 | 2.0e-10 |
| RSH | drain and source diffusion sheet resistance | Ω/□ | 0.0 | 10.0 |
| CJ | zero-bias bulk junction bottom cap. per sq-meter of junction area | F/m2 | 0.0 | 2.0e-4 |
| MJ | bulk junction bottom grading coeff. | - | 0.5 | 0.5 |
| CJSW | zero-bias bulk junction sidewall cap. per meter of junction perimeter | F/m | 0.0 | 1.0e-9 |
| MJSW | bulk junction sidewall grading coeff. | - | 0.50(level1) 0.33(level2, 3) | |
| JS | bulk junction saturation current per sq-meter of junction area | A/m2 | 1.0e-8 | |
| TOX | oxide thickness | meter | 1.0e-7 | 1.0e-7 |
| NSUB | substrate doping | 1/cm3 | 0.0 | 4.0e15 |
| NSS | surface state density | 1/cm2 | 0.0 | 1.0e10 |
| NFS | fast surface state density | 1/cm2 | 0.0 | 1.0e10 |
| name | parameter | units | default | example |
|---|---|---|---|---|
| TPG | type of gate material: +1 opp. to substrate -1 same as substrate 0 Al gate | - | 1.0 | |
| XJ | metallurgical junction depth | meter | 0.0 | 1µ |
| LD | lateral diffusion | meter | 0.0 | 0.8µ |
| UO | surface mobility | cm2/Vs | 600 | 700 |
| UCRIT | critical field for mobility degradation (MOS2 only) | V/cm | 1.0e4 | 1.0e4 |
| UEXP | critical field exponent in mobility degradation (MOS2 only) | - | 0.0 | 0.1 |
| UTRA | transverse field coeff. (mobility) (deleted for MOS2) | - | 0.0 | 0.3 |
| VMAX | maximum drift velocity of carriers | m/s | 0.0 | 5.0e4 |
| NEFF | total channel-charge (fixed and mobile) coefficient (MOS2 only) | - | 1.0 | 5.0 |
| KF | flicker noise coefficient | - | 0.0 | 1.0e-26 |
| AF | flicker noise exponent | - | 1.0 | 1.2 |
| FC | coefficient for forward-bias depletion capacitance formula | - | 0.5 | |
| DELTA | width effect on threshold voltage (MOS2 and MOS3) | - | 0.0 | 1.0 |
| THETA | mobility modulation (MOS3 only) | 1/V | 0.0 | 0.1 |
| ETA | static feedback (MOS3 only) | - | 0.0 | 1.0 |
| KAPPA | saturation field factor (MOS3 only) | - | 0.2 | 0.5 |
| TNOM | parameter measurement temperature | °C | 27 | 50 |
The level 4 and level 5 (BSIM1 and BSIM2) parameters are all values obtained from process characterization, and can be generated automatically. J. Pierret [4] describes a means of generating a 'process' file, and the program Proc2Mod provided with SPICE3 converts this file into a sequence of BSIM1 ".MODEL" lines suitable for inclusion in a SPICE input file. Parameters marked below with an * in the l/w column also have corresponding parameters with a length and width dependency. For example, VFB is the basic parameter with units of Volts, and LVFB and WVFB also exist and have units of Volt·µm. The formula
is used to evaluate the parameter for the actual device specified with
and
Note that unlike the other models in SPICE, the BSIM model is designed for use with a process characterization system that provides all the parameters, thus there are no defaults for the parameters, and leaving one out is considered an error. For an example set of parameters and the format of a process file, see the SPICE2 implementation notes[3].
For more information on BSIM2, see reference [5].
SPICE BSIM (level 4) parameters.
| name | parameter | units | l/w |
|---|---|---|---|
| VFB | flat-band voltage | V | * |
| PHI | surface inversion potential | V | * |
| K1 | body effect coefficient | V1/2 | * |
| K2 | drain/source depletion charge-sharing coefficient | - | * |
| ETA | zero-bias drain-induced barrier-lowering coefficient | - | * |
| MUZ | zero-bias mobility | cm2/V-s | |
| DL | shortening of channel | µm | |
| DW | narrowing of channel | µm | |
| U0 | zero-bias transverse-field mobility degradation coefficient | V-1 | * |
| U1 | zero-bias velocity saturation coefficient | µm/V | * |
| X2MZ | sens. of mobility to substrate bias at vds=0 | cm2/V2-s | * |
| X2E | sens. of drain-induced barrier lowering effect to substrate bias | V-1 | * |
| X3E | sens. of drain-induced barrier lowering effect to drain bias at Vds=Vdd | V-1 | * |
| X2U0 | sens. of transverse field mobility degradation effect to substrate bias | V-2 | * |
| X2U1 | sens. of velocity saturation effect to substrate bias | MmV-2 | * |
| MUS | mobility at zero substrate bias and at Vds=Vdd | cm2/V2-s | |
| X2MS | sens. of mobility to substrate bias at Vds=Vdd | cm2/V2-s | * |
| X3MS | sens. of mobility to drain bias at Vds=Vdd | cm2/V2-s | * |
| X3U1 | sens. of velocity saturation effect on drain bias at Vds=Vdd | MmV-2 | * |
| TOX | gate oxide thickness | µm | |
| TEMP | temperature at which parameters were measured | C | |
| VDD | measurement bias range | V | |
| CGDO | gate-drain overlap capacitance per meter channel width | F/m | |
| CGSO | gate-source overlap capacitance per meter channel width | F/m | |
| CGBO | gate-bulk overlap capacitance per meter channel length | F/m | |
| XPART | gate-oxide capacitance-charge model flag | - | |
| N0 | zero-bias subthreshold slope coefficient | - | * |
| NB | sens. of subthreshold slope to substrate bias | - | * |
| ND | sens. of subthreshold slope to drain bias | - | * |
| RSH | drain and source diffusion sheet resistance | Ω/□ | |
| JS | source drain junction current density | A/m2 | |
| PB | built in potential of source drain junction | V | |
| MJ | Grading coefficient of source drain junction | - | |
| PBSW | built in potential of source, drain junction sidewall | V | |
| MJSW | grading coefficient of source drain junction sidewall | - | |
| CJ | Source drain junction capacitance per unit area | F/m2 | |
| CJSW | source drain junction sidewall capacitance per unit length | F/m | |
| WDF | source drain junction default width | m | |
| DELL | Source drain junction length reduction | m |
XPART = 0 selects a 40/60 drain/source charge partition in saturation, while XPART=1 selects a 0/100 drain/source charge partition.
BSIM3 and BSIM4 (levels 8 and 14)
BSIM3 version 3.3.0 (level 8) and BSIM4 (level 14) are the Berkeley short-channel models used for modern processes. They have hundreds of model parameters, and like BSIM1 and BSIM2 are meant to be used with parameter sets from process characterization, usually supplied by the foundry. The parameters are listed on the BSIM3 and BSIM4 device pages; their meaning is described in the BSIM3 and BSIM4 manuals from the University of California, Berkeley.
The model's VERSION parameter should match the model: 3.3.0 for BSIM3, and 4.6.5 for BSIM4, which is the default (see the note on the BSIM4 page).
Foundry model files are usually HSPICE libraries, read with a .LIB line that names the process corner:
.lib 'c013hv32v.l' TT
HSPICE numbers BSIM3 as level 49 and BSIM4 as level 54, and Spice3f5 accepts both: LEVEL=49 is the same as LEVEL=8, and LEVEL=54 the same as LEVEL=14. HSPICE BSIM3 models are usually VERSION=3.24; they run with the BSIM3 3.3.0 code, with the warning This model is BSIM3v3.3.0; you specified a wrong version number. Parameters that are HSPICE extensions, such as XL, XW, ACM, the LOD stress parameters (SA0, SB0, KVTH0, ...) and TLEV, are ignored with an unrecognized parameter warning.
Model binning
As in HSPICE, a MOSFET may name a set of models rather than one: if a device's model name is, say, nch, and there are models named nch.1, nch.2, ... each with LMIN, LMAX, WMIN and WMAX parameters, the device uses the first of them whose range contains its L and W. Foundry libraries are usually written this way. Model names should not otherwise contain a . character.
The L and W compared are those after the .OPTIONS SCALE and GEOSHRINK are applied, so a shrink library's 40n device with GEOSHRINK=0.9 is binned, and simulated, as 36n. A device in a subcircuit that names binned models defined in the same subcircuit uses that subcircuit's models.
Parameters: MOSFET level 1 (Shichman-Hodges), MOSFET level 2 (MOS2), MOSFET level 3 (MOS3), MOSFET level 4 (BSIM1), MOSFET level 5 (BSIM2), MOSFET level 6 (MOS6), MOSFET level 8 (BSIM3 version 3.3.0), MOSFET level 14 (BSIM4)