Optimising with .optimise
Choosing a capacitor for a 5µs rise time.
An .optimise card varies C1 until the rise time measured by .meas is 5µs. The expected value is C1 = 5µs/(1kΩ·ln 9) = 2.276nF; the run then simulates the circuit with the optimised value.
- v(in)
- v(out)
Output
.optimise analysis tran 0.05u 20u vary c1 0.1n 10n target 5u risetime
Optimising 1 parameter, targeting 5u = risetime
1: mse = 7.85853e-12 c1=1e-09
2: mse = 2.3045e-12 c1=1.5849e-09
3: mse = 2.69374e-13 c1=2.5119e-09
8: mse = 6.61232e-15 c1=2.2387e-09
12: mse = 3.89031e-15 c1=2.3041e-09
14: mse = 9.78503e-17 c1=2.2712e-09
18: mse = 6.39544e-17 c1=2.2794e-09
20: mse = 8.76378e-19 c1=2.2753e-09
Converged after 46 simulations
Best mean square error = 8.76378e-19 (rms 9.36151e-10)
Parameter initial final min max
c1 capacitance 1e-09 2.2753e-09 1e-10 1e-08
risetime=4.99906e-06 FROM 1.24031e-06 TO 6.23937e-06
delay=1.57716e-06 FROM 1.0005e-06 TO 2.57766e-06
Capacitor: Fixed capacitor
device c1
model C
capacitanc 2.28e-09
i 2.65e-314
p 2.65e-314
The circuit: examples/optimise_card_demo.cir
optimise_card_demo.cir - .optimise cards driven by .meas results * A 1V pulse into an RC low pass vin in 0 pulse(0 1 1u 1n 1n 50u 100u) r1 in out 1k c1 out 0 1n .tran 0.05u 20u * Measure the 10%-90% rise time and the 50% delay .meas tran risetime TRIG v(out) VAL=0.1 RISE=1 TARG v(out) VAL=0.9 RISE=1 .meas tran delay TRIG v(in)=0.5 RISE=1 TARG v(out)=0.5 RISE=1 * Choose c1 for a 5us rise time: expect c1 = 5u/(1k*ln(9)) = 2.276n, * and then the delay is 5us*ln(2)/ln(9) = 1.577us .optimise analysis tran 0.05u 20u vary c1 0.1n 10n target 5u risetime .control * The run does the .optimise card first, then runs with the new c1, * printing the .meas results for it run show c1 plot v(in) v(out) .endc .end
Run it with spice optimise_card_demo.cir, or open it with File › Load netlist in the Qt window. The plots and output above were made by util/mkexamples.py, which runs the deck in batch mode. All examples