Cascaded RTL inverters

DC transfer curve and transient of two resistor-transistor logic inverters.

Two resistor-transistor logic inverters in cascade. The DC sweep shows the first inverter's transfer curve, and the transient shows a pulse passing through both stages.

Output

                     * rtlinv ckt - cascaded rtl inverters
              DC transfer characteristic Tue Sep 29 08:47:04  2026
--------------------------------------------------------------------------------
Index	sweep        v(3)         v(5)         
--------------------------------------------------------------------------------
0	0.000000e+00	4.622185e+00	2.665056e-01	
1	2.500000e-02	4.622185e+00	2.665056e-01	
2	5.000000e-02	4.622185e+00	2.665056e-01	
3	7.500000e-02	4.622185e+00	2.665056e-01	
4	1.000000e-01	4.622185e+00	2.665056e-01	
5	1.250000e-01	4.622185e+00	2.665056e-01	
6	1.500000e-01	4.622185e+00	2.665056e-01	
7	1.750000e-01	4.622185e+00	2.665056e-01	
8	2.000000e-01	4.622185e+00	2.665056e-01	
9	2.250000e-01	4.622185e+00	2.665056e-01	
10	2.500000e-01	4.622185e+00	2.665056e-01	
11	2.750000e-01	4.622185e+00	2.665056e-01	
12	3.000000e-01	4.622185e+00	2.665056e-01	
13	3.250000e-01	4.622185e+00	2.665056e-01	
14	3.500000e-01	4.622185e+00	2.665056e-01	
15	3.750000e-01	4.622185e+00	2.665056e-01	
16	4.000000e-01	4.622184e+00	2.665056e-01	
17	4.250000e-01	4.622184e+00	2.665056e-01	
18	4.500000e-01	4.622181e+00	2.665057e-01	
19	4.750000e-01	4.622176e+00	2.665057e-01	
20	5.000000e-01	4.622160e+00	2.665058e-01	
21	5.250000e-01	4.622121e+00	2.665061e-01	
22	5.500000e-01	4.622016e+00	2.665069e-01	
23	5.750000e-01	4.621742e+00	2.665091e-01	
24	6.000000e-01	4.621028e+00	2.665147e-01	
25	6.250000e-01	4.619189e+00	2.665290e-01	
26	6.500000e-01	4.614596e+00	2.665649e-01	
27	6.750000e-01	4.603869e+00	2.666492e-01	
28	7.000000e-01	4.581809e+00	2.668234e-01	
29	7.250000e-01	4.543818e+00	2.671271e-01	
30	7.500000e-01	4.489147e+00	2.675721e-01	
31	7.750000e-01	4.420497e+00	2.681451e-01	
32	8.000000e-01	4.341435e+00	2.688255e-01	
33	8.250000e-01	4.255111e+00	2.695947e-01	
34	8.500000e-01	4.163237e+00	2.704464e-01	
35	8.750000e-01	4.067545e+00	2.713721e-01	
36	9.000000e-01	3.969081e+00	2.723692e-01	
37	9.250000e-01	3.868550e+00	2.734382e-01	
38	9.500000e-01	3.766469e+00	2.745817e-01	
39	9.750000e-01	3.663221e+00	2.758039e-01	
40	1.000000e+00	3.559095e+00	2.771109e-01	
41	1.025000e+00	3.454314e+00	2.785106e-01	
42	1.050000e+00	3.349052e+00	2.800130e-01	
43	1.075000e+00	3.243447e+00	2.816308e-01	
44	1.100000e+00	3.137610e+00	2.833796e-01	
45	1.125000e+00	3.031633e+00	2.852791e-01	
46	1.150000e+00	2.925588e+00	2.873546e-01	
47	1.175000e+00	2.819539e+00	2.896385e-01	
48	1.200000e+00	2.713536e+00	2.921738e-01	
49	1.225000e+00	2.607624e+00	2.950186e-01	
50	1.250000e+00	2.501838e+00	2.982544e-01	
51	1.275000e+00	2.396211e+00	3.019999e-01	
52	1.300000e+00	2.290769e+00	3.064379e-01	
53	1.325000e+00	2.185536e+00	3.118709e-01	
54	1.350000e+00	2.080531e+00	3.188521e-01	
55	1.375000e+00	1.975771e+00	3.287169e-01	
56	1.400000e+00	1.871269e+00	3.450139e-01	
57	1.425000e+00	1.767026e+00	3.947596e-01	
58	1.450000e+00	1.662887e+00	7.886696e-01	
59	1.475000e+00	1.558984e+00	1.250481e+00	
60	1.500000e+00	1.455350e+00	1.718053e+00	
61	1.525000e+00	1.351982e+00	2.190635e+00	
62	1.550000e+00	1.248869e+00	2.667395e+00	
63	1.575000e+00	1.145987e+00	3.146700e+00	
64	1.600000e+00	1.043291e+00	3.625495e+00	
65	1.625000e+00	9.406769e-01	4.097337e+00	
66	1.650000e+00	8.378776e-01	4.545878e+00	
67	1.675000e+00	7.336355e-01	4.895323e+00	
68	1.700000e+00	6.255228e-01	4.996673e+00	
69	1.725000e+00	5.166017e-01	4.999972e+00	
70	1.750000e+00	4.251561e-01	4.999998e+00	
71	1.775000e+00	3.861180e-01	5.000000e+00	
72	1.800000e+00	3.685797e-01	5.000000e+00	
73	1.825000e+00	3.578053e-01	5.000000e+00	
74	1.850000e+00	3.501463e-01	5.000000e+00	
... (156 more lines)

The circuit: examples/rtlinv.cir

* rtlinv ckt - cascaded rtl inverters
*
vcc 6 0 5
vin 1 0 pulse(0 5 2ns 2ns 2ns 80ns)
rb1 1 2 10k
rc1 6 3 1k
q1 3 2 0 qnd
rb2 3 4 10k
q2 5 4 0 qnd
rc2 6 5 1k
.model qnd npn(bf=50 rb=70 rc=40 ccs=2pf tf=0.1ns tr=10ns cje=0.9pf
+   cjc=1.5pf pc=0.85 va=50)
*
.control
dc vin 0.0 2.5 0.025
print v(3) v(5)
plot v(3)
*
tran 2ns 200ns
print v(3) v(5)
plot v(3) v(5) v(1)
*.opt acct list node lvlcod=2
.endc
.end

Run it with spice rtlinv.cir, or open it with File › Load netlist in the Qt window. The plots and output above were made by util/mkexamples.py, which runs the deck in batch mode. All examples